1. Field of the Invention
The present invention is an improved system and method for reducing power dissipation in a semiconductor device by controlling the operation of the device through the use of an improved clock splitting arrangement. More particularly, the present invention uses an improved clock splitting circuit and logic to provide a better turnoff arrangement for a semiconductor storage device such as a master/slave latch where the turn off is accomplished earlier in the cycle which reduces power consumption and allows for a later turn off through the use of an early and late control signals based on early and late enable signals and logic to combine the control signals.
2. Background Art
As semiconductor devices get larger with more components fabricated on a single chip, it becomes important to reduce the power consumed and the heat generated by the chip. The power consumed in a factor of several different variables, including particularly the number of times that a semiconductor changes states. It would be therefore be desirable to turn off the semiconductor elements which are not being used, and turn them off as early as possible, while allowing for a decision that the semiconductor storage may not be needed still to be determined later in the cycle without losing the opportunity to turn off the semiconductor storage during that cycle.
Several systems for controlling power consumption in a semiconductor storage through the use of a clock splitter have been proposed. One of these involved the use of a slit clock to turn the storage device off to reduce the power consumed. Another system involved the use of wait states (or a lost cycle) when the devices were shut down (to avoid losing data). Still another approach slows down the clock (elongating the clocking signal) to allow for reduced power consumption in the semiconductor storage.
However, the prior art devices have the disadvantages that more power than necessary was still consumed by the semiconductor storage device, since the device was on and changing states more than necessary. Either the latch device was not turned off as early as possible to avoid consuming power or it was not turned off when it could have been turned off.
Further, in some systems, an additional cycle (a so-called "wait state") was required when the latches are turned on (or turned off), reducing performance of the system and the latches. Also, when the clock signal is elongated and therefore slowed down, the performance of the system (in cycles per unit of time) is undesirably reduced.
Accordingly, the prior art latch control circuits consumed more power than was necessary and could have been turned off without adverse effect on the logic.
Other disadvantages and limitations of the prior art systems will be apparent to those skilled in the art to which the invention applies in view of the following description of the preferred embodiment of the present invention, taken together with the accompanying drawings and the appended claims.